1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory comprising memory cells including diodes.
2. Description of the Background Art
Japanese Patent Laying-Open No. 2005-268370 discloses a crosspoint mask ROM (hereinafter referred to as a crosspoint diode ROM) having a plurality of memory cells, each including a diode, arranged in the form of a matrix. This crosspoint diode ROM is generally known as an exemplary memory.
FIG. 11 is a circuit diagram showing the structure of the conventional crosspoint diode ROM disclosed in the aforementioned Japanese Patent Laying-Open No. 2005-268370. Referring to FIG. 11, a plurality of word lines WL and a plurality of bit lines BL are arranged in a memory cell array 101 to intersect with each other in the conventional crosspoint diode ROM. The word lines WL and the bit lines BL are connected to a row decoder 106 and a column decoder 107 respectively, as described later.
The gate electrodes of a prescribed number of selection transistors 102 are connected to each word line WL at prescribed intervals. Each selection transistor 102 is constituted of a pair of n-channel transistors 102a and 102b. The pair of n-channel transistors 102a and 102b constituting each selection transistor 102 have a common source region. The source region of each selection transistor 102 (n-channel transistors 102a and 102b) is grounded through a corresponding source line S101. In the selection transistors 102 connected to the same word line WL, each pair of a first selection transistor 102 (n-channel transistor 102a) and a second selection transistor 102 (n-channel transistor 102b) adjacent to each other have a common drain region.
A plurality of memory cells 104 each including a diode 103 are provided in the memory cell array 101. The plurality of memory cells 104 are arranged in the form of a matrix along the plurality of word lines WL and the plurality of bit lines BL respectively, while a prescribed number of such memory cells 104 are connected to each word line WL through the corresponding selection transistor 102. More specifically, the cathodes of the prescribed number of diodes 103 are connected to the drain regions of the n-channel transistors 102 and 102b constituting the corresponding selection transistor 102. The anodes of the diodes 103 of prescribed memory cells 104 included in the plurality of memory cells 104 are connected to the corresponding bit lines BL respectively, while the anodes of the diodes 103 of the remaining memory cells 104 are not connected to the corresponding bit lines BL. In the conventional diode ROM, data held in each memory cell 104 is determined as “0” or “1” depending on whether or not the anode of the diode 103 of this memory cell 104 is connected to the corresponding bit line BL.
An address input circuit 105, a row decoder 106, a column decoder 107, a sense amplifier 108 serving as a data determination portion and an output circuit 109 are provided outside the memory cell array 101.
A data read operation of the conventional crosspoint diode ROM is now described. In the following description of the data read operation, it is assumed that a memory cell 104 (hereinafter referred to as a selected memory cell 104) enclosed with a broken line in FIG. 11 is selected.
In the data read operation of the conventional crosspoint diode ROM, the row decoder 106 changes the potentials of the plurality of word lines WL on the basis of address data received from the address input circuit 105. More specifically, the row decoder 106 converts the potential of the word line WL (hereinafter referred to as a selected word line WL) connected to the selected memory cell 104 and the potentials of the remaining word lines WL (hereinafter referred to as nonselected word lines WL) to high and low levels respectively. Thus, the selection transistors 102 connected to the selected word line WL enter ON-states, while the selection transistors 102 connected to the nonselected word lines WL enter OFF-states. In the memory cells 104 connected to the selected word line WL, therefore, the potentials of the cathodes of the diodes 103 lower to the GND level (low level) through the source lines S101 due to the ON-state of the corresponding selection transistors 102. In the memory cells 104 connected to the nonselected word lines WL, on the other hand, the cathodes of the diodes 103 enter floating states due to the OFF-states of the corresponding selection transistors 102.
The bit line BL (hereinafter referred to as a selected bit line BL) corresponding to the selected memory cell 104 is connected to the sense amplifier 108 through the column decoder 107 on the basis of the address data received from the address input circuit 105, while the remaining bit lines BL (hereinafter referred to as nonselected bit lines BL) enter floating states. The anode of the diode 103 included in the selected memory cell 104 is not connected to the selected bit line BL, whereby no low-level potential is transmitted to the sense amplifier 108. In this case, a load circuit (not shown) provided in the sense amplifier 108 holds the potential of the selected bit line BL at a high level. Thus, the sense amplifier 108 determines and amplifies the potential of the selected bit line BL, and thereafter outputs a low-level signal of reversed polarity with respect to the high-level potential of the selected bit line BL. Consequently, the output circuit 109 outputs the low-level signal received from the sense amplifier 108.
In the conventional crosspoint diode ROM disclosed in the aforementioned Japanese Patent Laying-Open No. 2005-268370, however, the nonselected bit lines BL enter floating states in the data read operation, whereby the potentials of the anodes of the nonselected memory cells 104 (diodes 103) connected to the nonselected bit lines BL tend to fluctuate. If the potential of the anode of any nonselected memory cell 104 (diode 103) lowers from a high level, for example, the potentials of the cathodes of the remaining nonselected memory cells 104 connected to the nonselected bit line BL connected with this nonselected memory cell 104 also disadvantageously lower from high levels. If the anode of the diode 103 of any nonselected memory cell 104 is connected to the selected bit line BL in the data read operation in this case, the potential of the selected bit line BL disadvantageously temporarily lowers through the low potential of the cathode of this nonselected memory cell 104 (diode 103). Consequently, the selected bit line BL requires a standby time for returning the potential to the high level. Thus, it is disadvantageously difficult to operate the diode ROM at a high speed.